Double patterning is a common multiple patterning technique in the semiconductor chip manufacturing industry. Multiple patterning enables chipmakers to image integrated circuit (IC) designs at 20 nanometers (nm) and below. Typically, double patterning refers to the litho-etch-litho-etch (LELE) pitch-splitting process, but double patterning also includes a spacer technique called self-aligned double patterning (SADP).
LELE requires two separate lithography and etch steps to define a single layer. LELE typically provides a 30% reduction in pitch, but LELE can be expensive, as it doubles the process steps in the lithography flow. Initially, this technique separates the layouts that cannot be printed with a single exposure, forming two lower-density masks. Then, it uses two separate exposure processes. This, in turn, forms two coarser patterns. They are combined and superimposed, which enables a single finer image on the wafer.
The SADP process uses one lithography step and additional deposition and etch steps to define a spacer-like feature. In the SADP process, the first step is to form mandrels on a substrate. Then, the pattern is covered with a deposition layer. The deposition layer is then etched, which, in turn, forms spacers. The top portion undergoes a chemical mechanical polishing (CMP) step, and the mandrels are removed, creating a mask using the remaining spacers. Only simple patterns are created in SADP or another version of the technology, self-aligned quadruple patterning (SAQP). In both SADP and SAQP, lone parallel lines are formed, followed by cuts.
Metal levels in DRAM and logic chips are more complex and cannot be created with SADP or SAQP. Instead, such metal layers are typically created by LELE. SADP and SAQP also have less design flexibility than LELE. Hole-type patterns are typically created by LELE-type technology as well. However, as noted above, LELE can be expensive since it doubles the process steps in the lithography flow. A less expensive, faster and simplified lithography flow is needed.